The present invention relates to a semiconductor device and a manufacturing method thereof, and for example, to an effective technique that can be applied to a semiconductor device having an electrically rewritable non-volatile memory and a manufacturing technique thereof.
EEPROMs (Electrically Erasable and Programmable Read Only Memories) and flash memories are widely used as non-volatile semiconductor memory devices in which information can be electrically written and erased. These non-volatile semiconductor memory devices (non-volatile memories) represented by the EEPROMs and flash memories that are widely used at present have a charge storage film, such as a conductive floating gate electrode or a trap insulating film that is surrounded by a silicon oxide film, below the gate electrode of a MOS (Metal Oxide Semiconductor) transistor. The non-volatile memory stores information by using the fact that the threshold value of a transistor varies depending on a state where charges are stored in the floating gate electrode or the trap insulating film.
The trap insulating film refers to an insulating film having trap levels in which charges can be stored, and a silicon nitride film, or the like, can be cited as one example of the trap insulating film. A non-volatile semiconductor memory device having a trap insulating film is operated as a storage element in which the threshold value of a MOS transistor is shifted by injecting and eliminating charges into/from the trap insulating film. A non-volatile semiconductor memory device, having such a trap insulating film as a charge storage film, is referred to as a MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistor, and is more excellent in data holding reliability because charges are stored in discrete trap levels, in comparison with the case where a conductive floating gate electrode is used as a charge storage film.
For example, Japanese Unexamined Patent Application Publication No. 2014-154790 (Patent Document 1) describes a technique in which both a memory cell including a MONOS type transistor and a MOS transistor that forms a peripheral circuit represented by a logic circuit are mounted in a mixed way.
Japanese Unexamined Patent Application Publication No. 2013-026494 (Patent Document 2) describes a technique with respect to an offset spacer and describes the fact that, when a silicon oxide film is used as the offset spacer particularly in a MISFET using a high dielectric constant film for a gate insulating film, variations are caused in the characteristics of the gate insulating film.
A MISFET (Metal Insulator Semiconductor Field Effect Transistor) that uses a high dielectric constant film containing a metal compound in a gate insulating film and uses a metal film in a gate electrode (hereinafter, referred to as an HKMG-MISFET) is used in a CMOS circuit of 32 nm node and beyond in which scaling has progressed. For example, in a semiconductor device in which a system including a non-volatile memory is formed, a MONOS type transistor and an HKMG-MISFET are mounted over the same semiconductor substrate in a mixed way. Herein, when an extension region of the MONOS type transistor or the HKMG-MISFET is formed, ions are injected in a state where an offset spacer is formed over the sidewall of the gate electrode, from the viewpoint of securing an effective channel length in order to suppress a short channel effect. In this case, it can be considered that an offset spacer to be used in the MONOS type transistor and that to be used in the HKMG-MISFET are formed by the same material, from the viewpoint of simplifying steps.
However, when the offset spacers are formed, for example, by a silicon oxide film, the same material, there is the concern that oxygen originating from the silicon oxide film that forms the offset spacer may enter a gate insulating film when a heat treatment for impurity activation is performed in the HKMG-MISFET, thereby possibly causing variations in the characteristics of the gate insulating film. In particular, in an HKMG-MISFET using a high dielectric constant film containing a metal compound in a gate insulating film, variations in the characteristics of the HKMG-MISFET, resulting from the entry of oxygen from an offset spacer into the gate insulating film, are revealed. From this, it is desirable not to use a silicon oxide film in the offset spacer in an HKMG-MISFET.
On the other hand, when offset spacers are formed, for example, by a silicon nitride film, the same material, the offset spacer including the silicon nitride film is formed to contact the sidewall of the gate electrode in the MONOS type transistor. In this case, the silicon nitride film has a charge storage function, and hence there is the possibility that a hot electron, generated when a writing operation is performed, may be trapped by the offset spacer including the silicon nitride film in the vicinity of the end portion of the gate electrode. And, there is the concern that, while writing operations are being repeated, charges are further stored in the offset spacer, thereby causing the threshold voltage in the vicinity of the end portion of the gate electrode to be increased. Such an increase in the threshold voltage will cause both degradation of a transconductance (gm), which is a ratio of a change in a drain current to a change in a gate voltage, and a decrease in a read-out current. From this, it is desirable not to use a silicon nitride film in an offset spacer in a MONOS type transistor.
From the facts mentioned above, it is desirable to devise offset spacers from the viewpoint of improving the characteristics of both a MONOS type transistor and an HKMG-MISFET.
Other challenges and new characteristics will become clear from the description and accompanying drawings of the present specification.
In a semiconductor device in one embodiment, an offset spacer in a MONOS type transistor is formed by a single layer film of a silicon oxide film or a laminated film including a silicon oxide film, while that in an HKMG-MISFET is formed by a silicon nitride film.
A manufacturing method of a semiconductor device in one embodiment includes the steps of: forming a silicon oxide film that contacts a side end portion of a charge storage film in a memory cell formation region; and forming a silicon nitride film that contacts a side end portion of a gate insulating film in a peripheral circuit formation region.